9
LTC4221
4221fa
U
U
PI FU CTIO S
GATE1 (Pin 4): Channel 1 Gate Drive. This pin is the high
side gate drive of an external N-channel MOSFET. When
V
ON1
< 0.821V, GATE1 is held low by a 100糀 current
source. When V
ON1
> 0.851V, an initial timing cycle is
followed by a start-up cycle when an internal charge pump
provides a 9.5糀 pull-up to ramp up GATE1 with inrush
current limiting. UVLO, overvoltage, overcurrent and ex-
ternally generated faults override the ON1 pin and pull
GATE1 low.
FB1
(Pin 5): V
OUT1
Feedback Input. FB1
monitors the
channel 1 output voltage with an external resistive divider.
When V
FB1
< 0.617V, the PWRGD1
pin is pulled low. When
V
FB1
> 0.822V, overvoltage is detected, the FAULT latch is
set and both GATEs are pulled low. The FB1
pin is also used
to control the channel 1 current limit during its start-up
cycle.
PWRGD1 (Pin 6): Channel 1 Power Good Output. PWRGD1
is pulled low when V
FB1
< 0.617V, during the initial timing
cycle or when the chip is in UVLO. An external pull-up is
required to generate a logic high at the open-drain PWRGD1
pin.
FAULT (Pin 7): Fault Status Input/Output. FAULT is a
bidirectional pin. As an input, pulsing V
FAULT
< 0.816V will
set the FAULT latch and bring the LTC4221 into the fault
state. As an output, FAULT is pulled high by an internal
3.8糀 pull-up under normal operating conditions. When
an overcurrent fault is detected by a SENSE pin or a
overvoltage fault detected by an FB pin, the FAULT latch is
set and the LTC4221 goes into the fault state. The FAULT
latch is reset by a UVLO or the ON1 pin being driven below
0.4V.
FILTER (Pin 8): Overcurrent Fault Timing Filter. The
FILTER pin requires an external capacitor to ground to
adjust the response time of the two slow comparators. The
FILTER pin can be left unconnected for a default slow
comparator response time of 15約.
TIMER (Pin 9): Analog System Timer. The TIMER pin
requires an external capacitor to ground to generate
timing delay cycles during start-up. The LTC4221s initial
and start-up timing cycles are controlled by C
TIMER
and the
internal current sources connected to the TIMER pin.
GND (Pin 10): Ground. Connect to a ground plane for
optimum performance.
PWRGD2 (Pin 11): Channel 2 Power Good Output. Similar
functionality as PWRGD1. Controlled by FB2.
FB2 (Pin 12): V
OUT2
Feedback Input. Similar functionality
as FB1. Monitors channel 2 output voltage, controls
PWRGD2 output and channel 2 start-up current limit.
GATE2 (Pin 13): Channel 2 Gate Drive. Similar functional-
ity as GATE1. Controls the gate drive of the channel 2
external N-channel MOSFET. ON2 controls GATE2 in the
same manner as ON1 controls GATE1. V
ON1
< 0.4V over-
rides conditions at ON2 and GATE2 is held low by a 100糀
current source. UVLO, overvoltage, overcurrent and exter-
nally generated faults override conditions at ON1 and ON2,
and pull GATE2 low.
SENSE2 (Pin 14): Channel 2 Current Sense Input. Similar
functionality as SENSE1. Monitors channel 2 load current
through R
SENSE2
placed in the supply path between V
CC2
and SENSE2. To disable the current limit and circuit
breaker function for channel 2, tie SENSE2 to V
CC2
.
V
CC2
(Pin 15): Channel 2 Positive Supply Input. V
CC2
can
range from 1V to 13.5V for normal operation but it must
be dV
CC1
. An undervoltage lockout circuit disables both
channels whenever the voltage at V
CC2
is less than 0.8V.
ON2 (Pin 16): Channel 2 On Input. GATE2 is pulled to
ground by a 100糀 current source when V
ON2
< 0.821V.
When V
ON2
> 0.851V, GATE2 ramps up after an initial
timing cycle.
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